The present invention relates to an arithmetic operation system for adding/subtracting binary data and, more particularly, to an arithmetic operation circuit which is suitable for high-speed processing of magnitude comparison between digital signals, and usable in an arithmetic logic unit (ALU) such as a microprocessor or a digital signal processor (DSP).
In comparing the magnitudes of two binary numbers, if the two binary numbers have positive and negative signs, they must be compared using their absolute values. For example, in detecting the peak of digital audio data, successive comparison between the absolute values of many digital audio sample data is repeatedly executed.
In this case, the successive comparison can be realized by calculating the absolute values of all the sample data in advance to compare the absolute values, or comparing the sample data while calculating the absolute value of each sample data every comparison.
Normally, to calculate the absolute value in the two's compliment expression employed as the expression form of data with a sign, the logic of the whole data is inverted depending on the sign bit of the data, and then "1" is added to the least significant bit (LSB). For this reason, an arithmetic operation circuit for adding "1" to the LSB is required in addition to an arithmetic operation circuit for performing comparison. Absolute values can be compared only when a total of two adders are prepared.
In a conventional absolute value comparator, upon reception of data X and Y with two signs (a, b) to be compared with each other, all the bits are inverted depending on respective sign bits a and b. Then, corresponding sign bits (a, b) are added to the least significant bits (LSB) of the all-bit-inverted data (X, Y). In this manner, the absolute values of binary data X and Y expressed by two's complements are calculated.
The magnitude relationship between calculated absolute values .vertline.X.vertline. and .vertline.Y.vertline. is determined by a no-sign comparator. If SF represents a sign flag (or arithmetic operation flag), this comparator outputs, as the comparison result, EQU SF=1 for .vertline.X.vertline..ltoreq..vertline.Y.vertline. EQU SF=0 for .vertline.X.vertline.&gt;.vertline.Y.vertline.
In the conventional circuit which calculates the absolute values of all input data in advance to compare them, the time required for arithmetic processing is long. Since processing of calculating the absolute values of data X and Y to be compared with each other must be performed for both X and Y, the total processing time is three times or more than the time required when data with no sign are compared.
When data before calculating its absolute value must be saved, a location for storing absolute value data .vertline.X.vertline. and .vertline.Y.vertline. must be ensured. The maximum memory capacity necessary for arithmetic processing is about two times the capacity required when data with no sign are compared.
In the method of comparing data while calculating the absolute value of each data every comparison, the necessary memory capacity does not increase. However, the processing time is three times or more than the time required when data with no sign are compared. In this method, if the processing time is shortened to about the time required when data with no sign are compared, the hardware amount (or processing ability required for the hardware) increases about three times.
In this manner, when the magnitudes of binary numbers expressed by two's complements are compared in the conventional arithmetic operation circuit, the processing time is undesirably long. If this processing time is shortened, the necessary hardware amount (necessary hardware processing ability) disadvantageously increases.